The present invention relates to a method and apparatus for the testing of wafers during the IC fabrication process and more particularly to a method and apparatus for the wireless testing of ICs on wafers.
In the Integrated Circuit (IC) manufacturing process, a plurality of ICs are formed upon the surface of a circular wafer by the successive deposition of various materials such as metal and oxide layers according to a design layout. After all of the layers have been deposited, the wafer is diced into separate ICs that are then packaged for sale. For quality assurance purposes any for evaluating the manufacturing process, the ICs are tested for proper operation before they are packaged for sale. However, if it could be determined before dicing and packaging that a defect had occurred in a particular IC, or in the manufacturing process, then substantial cost savings could be achieved by discarding the damaged IC before it is packaged or by discarding the entire wafer before it is diced and making corrections to the manufacturing process.
Conventional IC testing is done after all of the layers have been deposited on the wafer. Due to imperfections in the manufacturing process a certain amount of the ICs will be defective. For instance if the probability of a defect occurring during the deposition of a metallization layer is 1% then the probability of having defective ICs after 7 metallization layers have been deposited is 6.8% which is not insignificant since ICs are mass produced in large quantities. This is an investment on the part of the manufactures that could be mitigated by knowing errors in the manufacturing process before other manufacturing steps are done. Furthermore, because subsequent metallization layers affect the operation of previous metallization layers, it is difficult to ascertain at which point in the manufacturing process the defects occurred. Consequently, IC testing performed before all of the layers have been deposited can provide valuable information that can be used to discover faults in the IC or in the fabrication process. This is especially true for systematic faults such as faulty metal deposition. Test processes that are done before the IC is completed do exist but these tests are done destructively using physical probe contacts or capacitive coupling. Accordingly, none of those testing methods is satisfactory because of their destructive nature.
Current tests that are done once the IC is fabricated involve probing the IC via Input/Output (I/O) pads or special test pads. The results of these tests may disclose problems in the overall manufacturing process that extend to all the ICs which are fabricated, meanwhile operational tests of the ICs themselves may distinguish individual defective. ICs that can then be marked for disposal after dicing. The test method comprises powering up the ICs and using the probes to apply appropriate test signals and record the test result signals. The test result signals are then analyzed to insure that the IC is functioning correctly. This method, and other testing methods which make physical contact with the pads of the IC, require accurate placement of the wafer in relation to the probes which can be both an expensive and time-consuming process. Furthermore, physical contact with the wafer may damage the ICs.
Another difficulty with IC testing is that ICs are constantly increasing in density and complexity. This leads to a problem of visibility and accessibility when testing internal circuits within the ICs after the ICs have been fabricated. Furthermore, while the ICs are increasing in density and complexity, the number of I/O pins remains relatively constant or even limited by geometric constraints. This also contributes to difficulty in IC testing since the number of test signals which can be simultaneously sent to the IC is limited by the number of I/O pins. Likewise, the number of resulting test signals which are probed from the IC is limited.
The use of physical contact (i.e. using probes) in IC testing, after ICs have been fabricated, has another limitation in that the frequency of the test signals which are introduced to the IC is limited due to the physical contact. Current frequency limits are approximately 100 MHz. This frequency limitation puts a lower limit on the test time. Furthermore, this frequency limitation means that ICs are tested at only {fraction (1/10)}th or {fraction (1/100)}th of the clock frequency that is used during IC operation. Consequently, the test results may not accurately reflect how the IC will behave when it operates at its nominal clock frequency. In light of this information, it is becoming increasingly difficult to test or even access certain sub-circuits within the IC using existing test methods. With IC technology approaching 1 V operating levels, new test methods which use inductive coupling or radio frequency transmissions to transmit test data and receive test results are being developed. These tests involve fabricating small test circuits on the IC wafer. However, these test circuits must be small in size to reduce the overhead costs associated with fabricating these test circuits.
Schoellkopf (U.S. Pat. No. 6,16,607) discloses a test method that uses ring oscillators, oscillating at discrete frequencies, as test circuits. These ring oscillators are placed in the cutting path between the dies on the IC wafer. It is not certain how these test circuits are powered or controlled. The test circuits are connected to metallization layers at least two levels above the metallization levels that are used to fabricate the test circuit. In this manner, Schoellkopf is testing the propagation delay properties of the IC and whether the metal interconnects are intact. This test method measures the characteristics of the transistors in the test circuit as well as indirect measurement of the characteristics of the transistors of the adjacent ICs. However, Schoellkopf requires external probes for powering the test circuit, Furthermore, the test circuit does not allow for the measurement of the influence of the interconnection resistance and capacitance on the IC.
To be useful, the IC test method must work over a range of IC technologies (i.e. gate sizes measured in microns) and supply voltage levels. The IC test method, in particular the test circuits that are fabricated on the IC wafer, must therefore be scalable. It would also be beneficial if the test circuit were small in size so as to minimize the impact on chip real estate. Furthermore, since current state of the art ICs operate at very high speeds and have small dimensions, these ICs operate at the edge of analog behavior and conventional digital test methods may be insufficient. Consequently the IC test method should include characterization circuits to perform parametric IC testing in which certain parameters such as resistance are measured to provide an indication of the integrity of the IC manufacturing process. The parameters are important as they affect the performance of the IC. The IC test method should also test the IC at high speed.
The present invention comprises a test circuit for testing an integrated circuit on a wafer The invention further comprises an apparatus using the test circuit for testing an integrated circuit on a wafer. The apparatus comprises:
a) a test circuit formed on the wafer with the integrated circuit, the test circuit comprising:
i) a ring oscillator circuit;
ii) a plurality of sub-circuits coupled to the ring oscillator circuit;
iii) a control circuit to selectively couple the sub-circuits to the ring oscillator circuit, and
b) a test unit separate from the wafer, the test unit linked to the test circuit to transmit a signal to activate the test circuit. The test unit, when activated by the test unit, conducts a separate test of the integrated circuit for each sub-circuit selected by the control circuit.
The test conducted by the test circuit is a parametric test wherein the sub-circuits, when coupled to the ring oscillator circuit, change the frequency of oscillation of the ring oscillator circuit. The control circuit comprises a sequencer to selectively couple the sub-circuits to the ring oscillator circuit to produce a series of test states.
The test unit transmits a power signal (i.e. an RF power signal) that is sufficient to energize the test circuit.
The test circuit further includes at least one sub-circuit comprising a capacitive load to change the frequency of oscillation of the ring oscillator circuit. The capacitive load comprises at least one capacitor.
The test circuit further includes at least one sub-circuit comprising a capacitive load and a resistive load to change the frequency of oscillation of the ring oscillator circuit. The capacitive load comprises at least one capacitor and the resistive load comprises at least one resistor.
The test circuit further includes at least one sub-circuit comprising a delay element to change the frequency of oscillation of the ring oscillator circuit. The delay element may be at least one inverter wherein the inverter is a standard CMOS inverter.
The test circuit may be formed on the wafer with at least two metallization layers of the integrated circuit alternatively, the test circuit may be formed on the wafer with at least one metallization layer and one polysilicon layer of the integrated circuit.
The test circuit further comprises a transmitter circuit to transmit the test result signal from the test circuit to the test unit. The test result signal is the output of the ring oscillator circuit. Accordingly, the test unit comprises a receiver circuit to receive the test result signal from the test circuit. The test unit further comprises a circuit to analyze and display the test result signal. The analyzing circuit calculates a value of the parameter being tested The analyzing circuit may also calculate a ratio of the values or the parameters being tested.
The test circuit further comprises an antenna adapted to receive the signal from the test unit and a power supply circuit coupled to the antenna and adapted to provide power to the test circuit. The power supply circuit comprises a voltage rectifier coupled to the antenna, a voltage regulator coupled to the voltage rectifier and an energy storage element coupled to the voltage regulator, wherein the power supply circuit is adapted to provide a plurality of voltage levels to the test circuit.
The control circuit in the test circuit further comprises a second ring oscillator adapted to provide a first clock signal, and a divider coupled to the second ring oscillator and the sequencer and adapted to provide a second clock signal, wherein the second clock signal is provided to the sequencer so that the sequencer can provide a series of test state signals to the ring oscillator and plurality of sub-circuits.
The transmitter circuit in the test circuit further comprises a coupler which is coupled to the ring oscillator and the antenna and is adapted to selectively couple the output of the ring oscillator to the antenna for transmission of the test result signal to the last unit. The coupler may capacitively couple the test result signal to the antenna. Alternatively, the coupler may modulate the impedance of the antenna to transmit the test result signal to the test unit.
There may be plurality of test circuits that are placed on the wafer. The test unit may test each test circuit sequentially or test a plurality of the test circuits in parallel. Each test circuit may be formed adjacent to a die containing the integrated circuit. Alternatively, each test circuit may be formed on a die that contains the integrated circuit. Alternatively, each test circuit may be formed on a large percentage of dies on the wafer. Alternatively, each test circuit may be formed on dies near the edge of the wafer.
The invention also relates to a method of testing an integrated circuit on a wafer using a test circuit formed on the water with the integrated circuit, the test circuit comprising a ring oscillator circuit, a plurality of sub-circuits coupled to the ring oscillator circuit wherein each sub-circuit changes the frequency of oscillation of the ring oscillator circuit, and a control circuit to selectively couple the sub-circuits to the ring oscillator circuit, the method comprising;
(a) activating the test circuit
(b) sequentially coupling the sub-circuits to the ring oscillator circuit to selectively change the frequency of oscillation of the ring oscillator circuit;
(c) producing a test result signal in response to each sub-circuit selected by the control circuit, and,
(d) analyzing the test result signal to determine the frequency of oscillation
Each test conducted in the method is a parametric test. Accordingly, the method may further consist of calculating a value for the parameter being tested. Alternatively, the method may consist of calculating a ratio of values fur the parameter being tested.
The method further comprises effecting step (b) according to the steps of.
(e) providing a clock signal; and,
(f) generating a sequence of test states and state signals based on the clock signal to switchably couple the sub-circuits to the variable ring oscillator.
Step (d) of the method further comprises the steps of:
(g) coupling the test result signal to an antenna within the test circuit through a coupler in the test circuit; and,
(h) enabling and disabling the coupler to intermittently transmit the test result signal to a test unit to allow the test unit to synchronize to the test result signal and analyze the test result signal.
The method further comprises using at least one sub-circuit that comprises a capacitive load to change the frequency of operation of the ring oscillator circuit.
The method also further comprises using at least one sub-circuit that comprises a capacitive load and a resistive load to change the frequency of operation of the ring oscillator circuit.
The method also further comprises using at least one sub-circuit that comprises a delay element to change the frequency of oscillation of the ring oscillator circuit.
The method further comprises using a sequencer for the control circuit.
The method further comprises sequentially testing a plurality of test circuits which are formed on the wafer. Alternatively, the method further comprises testing the plurality of test circuits on the wafer in parallel.
Further objects and advantages of the invention will appear from the following description taken together with the accompanying drawings.